JPH0157439B2 - - Google Patents

Info

Publication number
JPH0157439B2
JPH0157439B2 JP4803983A JP4803983A JPH0157439B2 JP H0157439 B2 JPH0157439 B2 JP H0157439B2 JP 4803983 A JP4803983 A JP 4803983A JP 4803983 A JP4803983 A JP 4803983A JP H0157439 B2 JPH0157439 B2 JP H0157439B2
Authority
JP
Japan
Prior art keywords
storage
memory matrix
voltage
transistor
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4803983A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5942695A (ja
Inventor
Giiberu Burukuharuto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of JPS5942695A publication Critical patent/JPS5942695A/ja
Publication of JPH0157439B2 publication Critical patent/JPH0157439B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP58048039A 1982-03-24 1983-03-24 非揮発性で再プログラミング可能な蓄積セルを備えた集積メモリマトリツクス Granted JPS5942695A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP82102447.8 1982-03-24
EP82102447A EP0089397B1 (de) 1982-03-24 1982-03-24 Integrierte Speichermatrix mit nichtflüchtigen, umprogrammierbaren Speicherzellen

Publications (2)

Publication Number Publication Date
JPS5942695A JPS5942695A (ja) 1984-03-09
JPH0157439B2 true JPH0157439B2 (en]) 1989-12-05

Family

ID=8188946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58048039A Granted JPS5942695A (ja) 1982-03-24 1983-03-24 非揮発性で再プログラミング可能な蓄積セルを備えた集積メモリマトリツクス

Country Status (4)

Country Link
US (1) US4524429A (en])
EP (1) EP0089397B1 (en])
JP (1) JPS5942695A (en])
DE (1) DE3267750D1 (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018000608A (ja) * 2016-07-04 2018-01-11 株式会社三共 遊技機

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3587082T2 (de) * 1984-04-02 1993-06-03 Univ Leland Stanford Junior Speichersystem fuer analoge daten.
IT1221018B (it) * 1985-03-28 1990-06-21 Giulio Casagrande Dispositivo per verificare celle di memoria in funzione del salto di soglia ottenibile in fase di scrittura
EP0198935A1 (de) * 1985-04-23 1986-10-29 Deutsche ITT Industries GmbH Elektrisch umprogrammierbarer Halbleiterspeicher mit Redundanz
US4715014A (en) * 1985-10-29 1987-12-22 Texas Instruments Incorporated Modified three transistor EEPROM cell
JPS62177799A (ja) * 1986-01-30 1987-08-04 Toshiba Corp 半導体記憶装置
US6226200B1 (en) * 1999-11-17 2001-05-01 Motorola Inc. In-circuit memory array bit cell threshold voltage distribution measurement
US7850378B1 (en) * 2005-05-13 2010-12-14 Apple Inc. Webbed keyboard assembly
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127901A (en) * 1977-08-03 1978-11-28 Sperry Rand Corporation MNOS FET memory retention characterization test circuit
US4181980A (en) * 1978-05-15 1980-01-01 Electronic Arrays, Inc. Acquisition and storage of analog signals
US4223394A (en) * 1979-02-13 1980-09-16 Intel Corporation Sensing amplifier for floating gate memory devices
JPS57141097A (en) * 1981-02-25 1982-09-01 Toshiba Corp Storage circuit
US4441168A (en) * 1982-01-13 1984-04-03 Sperry Corporation Storage logic/array (SLA) circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018000608A (ja) * 2016-07-04 2018-01-11 株式会社三共 遊技機

Also Published As

Publication number Publication date
DE3267750D1 (en) 1986-01-16
JPS5942695A (ja) 1984-03-09
EP0089397A1 (de) 1983-09-28
US4524429A (en) 1985-06-18
EP0089397B1 (de) 1985-12-04

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